View CY2305CSXI-1T_1973233.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary cy2305c cy2309c 3.3v zero delay clock buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07672 rev. *f revised july 5, 2007 features 10 mhz to 100-133 mhz operating range, compatible with cpu and pci bus frequencies zero input and output propagation delay multiple low skew outputs one input drives five outputs (cy2305c) one input drives nine outputs, grouped as 4 + 4 + 1 (cy2309c) 50 ps typical cycle-cycle jitter (15 pf, 66 mhz) test mode to bypass phase locked loop (pll) (cy2309c) only, see ?select input decoding for cy2309c? on page 3 available in space saving 16-pin 150 mil soic or 4.4 mm tssop packages (cy2309c), and 8-pin, 150 mil soic package (cy2305c) 3.3v operation industrial temperature available functional description the cy2305c and cy2309c are die replacement parts for cy2305 and cy2309. the cy2309c is a low cost 3.3v zero delay buffer designed to distribute high speed clocks and is available in a 16-pin soic or tssop package. the cy2305c is an 8-pin version of the cy2309c. it accepts one reference input and drives out five low skew clocks. the -1h versions of each device operate up to 100-133 mhz frequencies and have higher drive than the -1 devices. all parts have on-chip plls which lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. the cy2309c has two banks of four outputs each that are controlled by the select inputs as shown in the ?select input decoding for cy2309c? on page 3. if all output clocks are not required, bankb is three-stated. the input clock is directly applied to the outputs by the select inputs for chip and system testing purposes. the cy2305c and cy2309c plls enter a power down mode when there are no rising edges on the ref input. in this state, the outputs are three-stated and the pll is turned off. this results in less than 12.0 a of current draw for commercial temperature devices and 25.0 a for industrial temperature parts. the cy2309c pll shuts down in one additional case as shown in the ?select input decoding for cy2309c? on page 3 . in the special case when s2:s1 is 1:0, the pll is bypassed and ref is output from dc to the maximum allowable frequency. the part behaves like a non-zero delay buffer in this mode and the outputs are not three-stated. the cy2305c or cy2309c is available in two or three different configurations as shown in the ?ordering information? on page 11. the cy2305c-1 or cy2309c-1 is the base part. the cy2305-1h or cy2309-1h is the high drive version of the -1. its rise and fall times are much faster than the -1s. logic block diagram for cy2309c pll mux select input ref s2 s1 clka1 clka2 clka3 clka4 clkb1 clkb2 clkb3 clkb4 decoding clkout [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 2 of 14 logic block diagram for cy2305c clkout ref clk4 pll clk1 clk2 clk3 [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 3 of 14 pinouts cy2309c table 1. pin definiti on - 16 pin soic/tssop figure 1. pin diagram - 16 pin soic/tssop pin signal description 1ref [1] input reference frequency 2 clka1 [2] buffered clock output, bank a 3 clka2 [2] buffered clock output, bank a 4v dd 3.3v supply 5 gnd ground 6 clkb1 [2] buffered clock output, bank b 7 clkb2 [2] buffered clock output, bank b 8s2 [3] select input, bit 2 9s1 [3] select input, bit 1 10 clkb3 [2] buffered clock output, bank b 11 clkb4 [2] buffered clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 [2] buffered clock output, bank a 15 clka4 [2] buffered clock output, bank a 16 clkout [2] buffered output, internal feedback on this pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 clkout clka4 clka3 v dd gnd clkb4 clkb3 s1 soic/tssop top view cy2309c notes 1. weak pull down. 2. weak pull down on all outputs. 3. weak pull ups on these inputs. 4. this output is driven and has an internal feedback for the p ll. the load on this output is adjusted to change the skew betwee n the reference and output. table 2. select input decoding for cy2309c s2 s1 clock a1?a4 clock b1?b4 clkout [4] output source pll shutdown 0 0 three state three state driven pll n 0 1 driven three state driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 4 of 14 cy2305c zero delay and skew control all outputs should be uniformly loaded to achieve zero delay bet ween the input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input or output delay. for applications requiring zero input or ou tput delay, all outputs including clkout ar e equally loaded. even if clkout is not u sed, it must have a capacitive load equal to that on other outputs for obtaining zero input or output delay. for zero output or output skew, all output s are loaded equally. for further information refer to the application note entitled ?cy2305 and cy2309 as pci and sdram buffers?. figure 2. pin diagram - 8 pin soic table 3. pin description - 8 pin soic pin signal description 1ref [1] input reference frequency 2clk2 [2] buffered clock output 3clk1 [2] buffered clock output 4 gnd ground 5clk3 [2] buffered clock output 6v dd 3.3v supply 7clk4 [2] buffered clock output 8clkout [2] buffered clock output, internal feedback on this pin 1 2 3 4 5 8 7 6 ref clk2 clk1 gnd v dd clkout clk4 clk3 soic top view cy2305c [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 5 of 14 absolute maximum conditions supply voltage to ground potentia l................?0.5v to +4.6v dc input voltage (except ref) ............ ?0.5v to v dd + 0.5v dc input voltage ref ........................... ?0.5v to v dd + 0.5v storage temperature ................................. ?65c to +150c junction temperature ................................................. 150c static discharge voltage (per mil-std-883, method 3015) .. ............. ............ > 2,000v operating conditions for cy 2305csxc-xx and cy2309csxc-xx operating conditions table for cy2305csxc-xx and cy2309csxc-xx commercial temperature devices. parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (amb ient temperature) 0 70 c c l load capacitance, below 100 mhz 30 pf c l load capacitance, from 100 mhz to 133 mhz 10 pf c in input capacitance 7 pf t pu power up time for all v dd s to reach minimum specified voltage (power ramps are monotonic) 0.05 50 ms electrical characteristics for cy2305csxc-xx and cy2309csxc-xx electrical characteristics table for cy2305csxc-x x and cy2309csxc-xx commercial temperature devices. parameter description test conditions min max unit v il input low voltage [5] ?0.3 0.8 v v ih input high voltage [5] 2.0 v dd + 0.3 v i il input low current v in = 0v ? 50 a i ih input high current v in = v dd ? 100 a v ol output low voltage [6] i ol = 8 ma (?1) i oh = 12 ma (?1h) ?0.4v v oh output high voltage [6] i oh = ?8 ma (?1) i ol = ?12 ma (?1h) 2.4 ? v i dd (pd mode) power down supply current ref = 0 mhz ? 12.0 a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd ?32ma notes 5. .ref input has a threshold voltage of v dd /2. 6. parameter is guaranteed by design and char acterization. not 100% tested in production. [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 6 of 14 switching characteristics fo r cy2305csxc-xx a nd cy2309csxc-xx switching characteristics table for cy2305csxc-1 and cy2309csxc -1 commercial temperature devices. all parameters are specified with loaded outputs. parameter name test cond itions min typ max unit t 1 output frequency 30 pf load 10 pf load 10 10 ?100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % t 3 rise time [6] measured between 0.8v and 2.0v ? ? 2.25 ns t 4 fall time [6] measured between 0.8v and 2.0v ? ? 2.25 ns t 5 output to output skew [6] all outputs equally loaded ? ? 200 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 ? 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309c device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices ?0700ps t j cycle to cycle jitter, peak [6] measured at 66.67 mhz, loaded outputs ? 50 175 ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin ??1.0ms switching characteristics table for cy2305csxc-1h and cy2309csxc-1h commercial temperature devices. all parameters are specified with loaded outputs. parameter name descrip tion min typ max unit t 1 output frequency 30-pf load 10-pf load 10 10 ?100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle [6] = t 2 t 1 measured at 1.4v, f out < 50.0 mhz 45.0 50.0 55.0 % t 3 rise time [6] measured between 0.8v and 2.0v ? ? 1.5 ns t 4 fall time [6] measured between 0.8v and 2.0v ? ? 1.5 ns t 5 output to output skew [6] all outputs equally loaded ? ? 200 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 ? 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309c device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices ?0700ps t 8 output slew rate [6] measured between 0.8v and 2.0v using test circuit #2 1??v/ns t j cycle to cycle jitter, peak [6] measured at 66.67 mhz, loaded outputs ? ? 175 ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin ??1.0ms [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 7 of 14 operating conditions for cy2305csxi-xx a nd cy2309csxi-xx operating conditions table for cy2305csxi-xx and cy2309csxi-xx industrial temperature devices. parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperat ure (ambient temperature) ?40 85 c c l load capacitance, below 100 mhz ? 30 pf c l load capacitance, from 100 mhz to 133 mhz ? 10 pf c in input capacitance ? 7 pf electrical characteristics for cy2305csxi-xx and cy2309csxi-xx electrical characteristics table for cy2305csxi- xx and cy2309csxi-xx industr ial temperature devices. parameter description test conditions min max unit v il input low voltage [5] ?0.3 0.8 v v ih input high voltage [5] 2.0 v dd + 0.3 v i il input low current v in = 0v ? 50.0 a i ih input high current v in = v dd ? 100.0 a v ol output low voltage [6] i ol = 8 ma (?1) i oh =12 ma (?1h) ?0.4v v oh output high voltage [6] i oh = ?8 ma (?1) i ol = ?12 ma (?1h) 2.4 ? v i dd (pd mode) power down supply current ref = 0 mhz ? 25.0 a i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd ?35ma [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 8 of 14 switching characteristics for cy2305csxi-xx and cy2309csxi-xx switching characteristics table for cy2305csxi-1and cy2309csxi-1 i ndustrial temperature devices. all parameters are specified with loaded outputs. parameter name test cond itions min typ max unit t 1 output frequency 30 pf load 10 pf load 10 10 100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % t 3 rise time [6] measured between 0.8v and 2.0v ? ? 2.25 ns t 4 fall time [6] measured between 0.8v and 2.0v ? ? 2.25 ns t 5 output to output skew [6] all outputs equally loaded ? ? 200 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 ? 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309c device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices ?0700ps t j cycle to cycle jitter, peak [6] measured at 66.67 mhz, loaded outputs ?50175ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin ??1.0ms switching characteristics table for cy2305csxi-1h and cy2309csxi-1 h industrial temperature device. all parameters are specified with loaded outputs. parameter name descrip tion min typ max unit t 1 output frequency 30 pf load 10 pf load 10 10 ? 100 133.33 mhz mhz duty cycle [6] = t 2 t 1 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle [6] = t 2 t 1 measured at 1.4v, f out < 50.0 mhz 45.0 50.0 55.0 % t 3 rise time [6] measured between 0.8v and 2.0v ? ? 1.5 ns t 4 fall time [6] measured between 0.8v and 2.0v ? ? 1.5 ns t 5 output to output skew [6] all outputs equally loaded ? ? 200 ps t 6a delay, ref rising edge to clkout rising edge [6] measured at v dd /2 ? 0 350 ps t 6b delay, ref rising edge to clkout rising edge [6] measured at v dd /2. measured in pll bypass mode, cy2309c device only. 158.7ns t 7 device to device skew [6] measured at v dd /2 on the clkout pins of devices ? 0 700 ps t 8 output slew rate [6] measured between 0.8v and 2.0v using test circuit #2 1? v/ns t j cycle to cycle jitter, peak [6] measured at 66.67 mhz, loaded outputs ? ? 175 ps t lock pll lock time [6] stable power supply, valid clock presented on ref pin ??1.0ms [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 9 of 14 switching waveforms figure 3. duty cycle timing figure 4. all outputs rise/fall time figure 5. ou tput-output skew figure 6. input-output propagation delay figure 7. device-device skew t 1 t 2 1.4v 1.4v 1.4v output t 3 3.3v 0v 0.8v 2.0v 2.0v 0.8v t 4 1.4v 1.4v t 5 output output v dd /2 t 6 input output v dd /2 v dd /2 v dd /2 t 7 clkout, device 1 clkout, device 2 [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 10 of 14 test circuits 0.1 f v dd 0.1 f v dd clk out c load outputs gnd gnd 0.1 f v dd 0.1 f v dd 10 pf outputs gnd gnd 1 k 1 k test circuit # 1 test circuit # 2 for parameter t 8 (output slew rate) on -1h devices [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 11 of 14 ordering information ordering code package type operating range pb-free - cy2305c cy2305csxc-1 8-pin 150 mil soic commercial cy2305csxc-1t 8-pin 150 mil soic ? tape and reel commercial cy2305csxc-1h 8-pin 150 mil soic commercial cy2305csxc-1ht 8-pin 150 mil soic ? tape and reel commercial cy2305csxi-1 8-pin 150 mil soic industrial CY2305CSXI-1T 8-pin 150 mil soic ? tape and reel industrial cy2305csxi-1h 8-pin 150 mil soic industrial cy2305csxi-1ht 8-pin 150 mil soic ? tape and reel industrial pb-free- cy2309c cy2309csxc-1 16-pin 150 mil soic commercial cy2309csxc-1t 16-pin 150 mil soic ? tape and reel commercial cy2309csxc-1h 16-pin 150 mil soic commercial cy2309csxc-1ht 16-pin 150 mil soic ? tape and reel commercial cy2309csxi-1 16-pin 150 mil soic industrial cy2309csxi-1t 16-pin 150 mil soic ? tape and reel industrial cy2309csxi-1h 16-pin 150 mil soic industrial cy2309csxi-1ht 16-pin 150 mil soic ? tape and reel industrial cy2309czxc-1 16-pin 4.4 mm tssop commercial cy2309czxc-1t 16-pin 4.4 mm tssop ? tape and reel commercial cy2309czxc-1h 16-pin 4.4 mm tssop commercial cy2309czxc-1ht 16-pin 4.4 mm tssop ? tape and reel commercial cy2309czxi-1 16-pin 4.4 mm tssop industrial cy2309czxi-1t 16-pin 4.4 mm tssop ? tape and reel industrial cy2309czxi-1h 16-pin 4.4 mm tssop industrial cy2309czxi-1ht 16-pin 4.4 mm tssop ? tape and reel industrial [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 12 of 14 package drawing and dimensions figure 8. 8-pin (150 mil) soic s8 figure 9. 16-pin (150 mil) soic s16 seating plane pin1id 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. dimensions in inches[mm] min. max. 0~8 0.016[0.406] 0.010[0.254] x 45 2. pin 1 id is optional, round on single leadframe rectangular on matrix leadframe 0.004[0.102] 1 4 58 3. reference jedec ms-012 part # s08.15 standard pkg. sz08.15 lead free pkg. 4. package weight 0.07gms pin 1 id 0~8 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms [+] feedback
preliminary cy2305c cy2309c document number: 38-07672 rev. *f page 13 of 14 figure 10. 16-pin tssop 4.40 mm body z16.173 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05gms [+] feedback
document number: 38-07672 rev. *f revised july 5, 2007 page 14 of 14 psoc designer?, programmable system-on-chip ?, and psoc express? are trademarks and psoc? is a registered trademark of cypress s emiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i 2 c components from cypress or one of its sublicense d associated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. all products and company names mentioned in this document may be the trademarks of their respective holders. preliminary cy2305c cy2309c ? cypress semiconductor corporation, 2007. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cy2305c cy2309c 3.3v zero delay clock buffer document number: 38-07672 rev. ecn no. issue date orig. of change description of change ** 224421 see ecn rgl new datasheet *a 268571 see ecn rgl added bullet for 5v tolerant inputs in the features *b 276453 see ecn rgl minor change: moved one sent ence from the features to the functional description *c 303063 see ecn rgl updated datasheet as per characterization data *d 318315 see ecn rgl datasheet rewrite *e 344815 see ecn rgl minor error: corrected the header of all the ac/dc tables with the right part numbers. *f 1279889 see ecn kvm changed title from ?low cost 3.3v zero delay buffer? to ?3.3v zero delay clock buffer? specified the vil minimum value to -0.3v specified the vih maximum value to vdd + 0.3v changed dc input voltage (ref) maxi mum value in absolute maximum section removed references to 5v tolerant inputs (pages 1 and 2) removed pentium comp atibility reference added cy2305c block diagram added ?peak? to the jitter specifications changed typical jitter from 75 ps to 50 ps for standard drive devices for standard drive devices, tightened ri se/fall times from 2.5 ns to 2.25 ns tightened cycle-to-cycle jitter from 200 ps to 175 ps tightened output-to-output skew from 250 ps to 200 ps [+] feedback

▲Up To Search▲

Price & Availability of CY2305CSXI-1T

	To Download CY2305CSXI-1T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .